Aarch64
AARCH64_BIT_SHIFT_MAP: Dict[int, Callable[[int, int, int], int]] = {ARM64_SFT_LSL: bit_math.logical_shift_left, ARM64_SFT_LSR: bit_math.logical_shift_right, ARM64_SFT_ASR: bit_math.arithmetic_shift_right, ARM64_SFT_ROR: bit_math.rotate_right} module-attribute ¶
AARCH64_EMULATED_ANNOTATIONS = CONDITIONAL_SELECT_INSTRUCTIONS | {ARM64_INS_SXTB, ARM64_INS_SXTH, ARM64_INS_SXTW, ARM64_INS_UXTB, ARM64_INS_UXTH, ARM64_INS_UXTW, ARM64_INS_RBIT, ARM64_INS_CLS, ARM64_INS_CLZ, ARM64_INS_BFXIL, ARM64_INS_UBFIZ, ARM64_INS_UBFM, ARM64_INS_UBFX, ARM64_INS_SBFIZ, ARM64_INS_SBFM, ARM64_INS_SBFX, ARM64_INS_BFI, ARM64_INS_NEG, ARM64_INS_NEGS, ARM64_INS_REV, ARM64_INS_BIC, ARM64_INS_BICS} module-attribute ¶
AARCH64_EXCLUSIVE_STORE_INSTRUCTIONS = {ARM64_INS_STXRB: 1, ARM64_INS_STXRH: 2, ARM64_INS_STXR: None, ARM64_INS_STLXRB: 1, ARM64_INS_STLXRH: 2, ARM64_INS_STLXR: None} module-attribute ¶
AARCH64_EXTEND_MAP: Dict[int, Callable[[int], int]] = {ARM64_EXT_UXTB: lambda x: x & 1 << 8 - 1, ARM64_EXT_UXTH: lambda x: x & 1 << 16 - 1, ARM64_EXT_UXTW: lambda x: x & 1 << 32 - 1, ARM64_EXT_UXTX: lambda x: x, ARM64_EXT_SXTB: lambda x: bit_math.to_signed(x, 8), ARM64_EXT_SXTH: lambda x: bit_math.to_signed(x, 16), ARM64_EXT_SXTW: lambda x: bit_math.to_signed(x, 32), ARM64_EXT_SXTX: lambda x: bit_math.to_signed(x, 64)} module-attribute ¶
AARCH64_MATH_INSTRUCTIONS = {ARM64_INS_ADD: '+', ARM64_INS_ADDS: '+', ARM64_INS_SUB: '-', ARM64_INS_SUBS: '-', ARM64_INS_AND: '&', ARM64_INS_ANDS: '&', ARM64_INS_ORR: '&', ARM64_INS_ASR: '>>s', ARM64_INS_ASRV: '>>s', ARM64_INS_EOR: '^', ARM64_INS_LSL: '<<', ARM64_INS_LSLV: '<<', ARM64_INS_LSR: '>>', ARM64_INS_LSRV: '>>', ARM64_INS_UDIV: '/', ARM64_INS_SDIV: '/', ARM64_INS_SMULH: '*', ARM64_INS_SMULL: '*', ARM64_INS_UMULH: '*', ARM64_INS_UMULL: '*', ARM64_INS_MUL: '*'} module-attribute ¶
AARCH64_SINGLE_LOAD_INSTRUCTIONS: Dict[int, int | None] = {ARM64_INS_LDRB: 1, ARM64_INS_LDURB: 1, ARM64_INS_LDRSB: -1, ARM64_INS_LDURSB: -1, ARM64_INS_LDRH: 2, ARM64_INS_LDURH: 2, ARM64_INS_LDRSH: -2, ARM64_INS_LDURSH: -2, ARM64_INS_LDURSW: -4, ARM64_INS_LDRSW: -4, ARM64_INS_LDUR: None, ARM64_INS_LDR: None, ARM64_INS_LDTRB: 1, ARM64_INS_LDTRSB: -1, ARM64_INS_LDTRH: 2, ARM64_INS_LDTRSH: -2, ARM64_INS_LDTRSW: -4, ARM64_INS_LDTR: None, ARM64_INS_LDXRB: 1, ARM64_INS_LDXRH: 2, ARM64_INS_LDXR: None, ARM64_INS_LDARB: 1, ARM64_INS_LDARH: 2, ARM64_INS_LDAR: None} module-attribute ¶
AARCH64_SINGLE_STORE_INSTRUCTIONS: Dict[int, int | None] = {ARM64_INS_STRB: 1, ARM64_INS_STURB: 1, ARM64_INS_STRH: 2, ARM64_INS_STURH: 2, ARM64_INS_STUR: None, ARM64_INS_STR: None, ARM64_INS_STTRB: 1, ARM64_INS_STTRH: 2, ARM64_INS_STTR: None, ARM64_INS_STLRB: 1, ARM64_INS_STLRH: 2, ARM64_INS_STLR: None} module-attribute ¶
CONDITIONAL_SELECT_INSTRUCTIONS = {ARM64_INS_CSEL, ARM64_INS_CSINC, ARM64_INS_CSINV, ARM64_INS_CSNEG, ARM64_INS_CSET, ARM64_INS_CSETM, ARM64_INS_CINC, ARM64_INS_CINV, ARM64_INS_CNEG} module-attribute ¶
assistant = DisassemblyAssistant('aarch64') module-attribute ¶
DisassemblyAssistant ¶
Bases: DisassemblyAssistant
annotation_handlers: Dict[int, Callable[[PwndbgInstruction, Emulator], None]] = {ARM64_INS_MOV: self._common_move_annotator, ARM64_INS_MOVK: self._common_generic_register_destination, ARM64_INS_ADR: self._common_generic_register_destination, ARM64_INS_ADRP: self._handle_adrp, ARM64_INS_CMP: self._common_cmp_annotator_builder('cpsr', '-'), ARM64_INS_CMN: self._common_cmp_annotator_builder('cpsr', '+'), ARM64_INS_TST: self._common_cmp_annotator_builder('cpsr', '&'), ARM64_INS_CCMP: self._common_cmp_annotator_builder('cpsr', ''), ARM64_INS_CCMN: self._common_cmp_annotator_builder('cpsr', '')} instance-attribute ¶
__init__(architecture) ¶
resolve_condition(condition, cpsr) ¶
Given a condition and the NZCV flag bits, determine when the condition is satisfied
The condition is a Capstone constant