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riscv ¤

Classes:

Attributes:

RISCV_LOAD_INSTRUCTIONS module-attribute ¤

RISCV_LOAD_INSTRUCTIONS = {
    RISCV_INS_LB: -1,
    RISCV_INS_LH: -2,
    RISCV_INS_LW: -4,
    RISCV_INS_LBU: 1,
    RISCV_INS_LHU: 2,
    RISCV_INS_LWU: 4,
    RISCV_INS_LD: 8,
    RISCV_INS_C_LW: -4,
    RISCV_INS_C_LWSP: -4,
    RISCV_INS_C_LD: 8,
    RISCV_INS_C_LDSP: 8,
}

RISCV_STORE_INSTRUCTIONS module-attribute ¤

RISCV_STORE_INSTRUCTIONS = {
    RISCV_INS_SB: 1,
    RISCV_INS_SH: 2,
    RISCV_INS_SW: 4,
    RISCV_INS_SD: 8,
    RISCV_INS_C_SW: 4,
    RISCV_INS_C_SWSP: 4,
    RISCV_INS_C_SD: 8,
    RISCV_INS_C_SDSP: 8,
}

RISCV_MATH_INSTRUCTIONS module-attribute ¤

RISCV_MATH_INSTRUCTIONS = {
    RISCV_INS_ADDI: "+",
    RISCV_INS_ADD: "+",
    RISCV_INS_C_ADDI: "+",
    RISCV_INS_C_ADD: "+",
    RISCV_INS_SUB: "-",
    RISCV_INS_C_SUB: "-",
    RISCV_INS_XORI: "^",
    RISCV_INS_XOR: "^",
    RISCV_INS_C_XOR: "^",
    RISCV_INS_ORI: "|",
    RISCV_INS_OR: "|",
    RISCV_INS_C_OR: "|",
    RISCV_INS_ANDI: "&",
    RISCV_INS_C_ANDI: "&",
    RISCV_INS_AND: "&",
    RISCV_INS_C_AND: "&",
    RISCV_INS_SLLI: "<<",
    RISCV_INS_C_SLLI: "<<",
    RISCV_INS_SLL: "<<",
    RISCV_INS_SRLI: ">>",
    RISCV_INS_C_SRLI: ">>",
    RISCV_INS_SRL: ">>",
    RISCV_INS_SRAI: ">>s",
    RISCV_INS_C_SRAI: ">>s",
    RISCV_INS_SRA: ">>s",
    RISCV_INS_MUL: "*",
    RISCV_INS_MULH: "*",
    RISCV_INS_MULHSU: "*",
    RISCV_INS_MULHU: "*",
    RISCV_INS_DIV: "/",
    RISCV_INS_DIVU: "/",
    RISCV_INS_REM: "%",
    RISCV_INS_REMU: "%",
    RISCV_INS_C_ADDI4SPN: "+",
    RISCV_INS_C_ADDI16SP: "+",
    RISCV_INS_ADDIW: "+",
    RISCV_INS_ADDW: "+",
    RISCV_INS_SUBW: "-",
    RISCV_INS_SLLIW: "<<",
    RISCV_INS_SLLW: "<<",
    RISCV_INS_SRLIW: ">>",
    RISCV_INS_SRLW: ">>",
    RISCV_INS_SRAIW: ">>s",
    RISCV_INS_SRAW: ">>s",
    RISCV_INS_MULW: "*",
    RISCV_INS_DIVW: "/",
    RISCV_INS_DIVUW: "/",
    RISCV_INS_REMW: "%",
    RISCV_INS_REMUW: "%",
    RISCV_INS_C_ADDIW: "+",
    RISCV_INS_C_ADDW: "+",
    RISCV_INS_C_SUBW: "-",
}

RISCV_EMULATED_ANNOTATIONS module-attribute ¤

RISCV_EMULATED_ANNOTATIONS = {
    RISCV_INS_SLT,
    RISCV_INS_SLTU,
    RISCV_INS_SLTI,
    RISCV_INS_SLTIU,
}

RISCVDisassemblyAssistant ¤

RISCVDisassemblyAssistant(architecture)

Bases: DisassemblyAssistant

Methods:

  • enhance –

    Enhance the instruction - resolving branch targets, conditionals, and adding annotations

  • can_reason_about_process_state –

    Determine if the program counter of the process equals the address of the instruction being enhanced.

  • dump –

    Debug-only method.

Attributes:

architecture instance-attribute ¤

architecture = architecture

annotation_handlers instance-attribute ¤

annotation_handlers: Dict[
    int, Callable[[PwndbgInstruction, Emulator], None]
] = {
    RISCV_INS_AUIPC: _auipc_annotator,
    RISCV_INS_C_MV: _common_move_annotator,
    RISCV_INS_C_LI: _common_move_annotator,
    RISCV_INS_LUI: _lui_annotator,
    RISCV_INS_C_LUI: _lui_annotator,
}

op_handlers instance-attribute ¤

op_handlers: dict[
    int, Callable[[PwndbgInstruction, EnhancedOperand, Emulator], int | None]
] = {
    CS_OP_IMM: _parse_immediate,
    CS_OP_REG: _parse_register,
    CS_OP_MEM: _parse_memory,
}

op_names instance-attribute ¤

op_names: dict[
    int, Callable[[PwndbgInstruction, EnhancedOperand], str | None]
] = {
    CS_OP_IMM: _immediate_string,
    CS_OP_REG: _register_string,
    CS_OP_MEM: _memory_string,
}

enhance ¤

enhance(instruction: PwndbgInstruction, emu: Emulator = None) -> None

Enhance the instruction - resolving branch targets, conditionals, and adding annotations

This is the only public method that should be called on this object externally.

can_reason_about_process_state ¤

can_reason_about_process_state(instruction: PwndbgInstruction) -> bool

Determine if the program counter of the process equals the address of the instruction being enhanced. If so, it means we can safely reason and read from registers and memory to enhance values that we can add to the annotation string. This becomes relevent when NOT emulating, and is meant to allow more details when the PC is at the instruction being enhanced

dump ¤

dump(instruction: PwndbgInstruction)

Debug-only method.