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aarch64 ¤

Classes:

Functions:

  • resolve_condition –

    Given a condition and the NZCV flag bits, determine when the condition is satisfied

Attributes:

AARCH64_SINGLE_LOAD_INSTRUCTIONS module-attribute ¤

AARCH64_SINGLE_LOAD_INSTRUCTIONS: dict[int, int | None] = {
    ARM64_INS_LDRB: 1,
    ARM64_INS_LDURB: 1,
    ARM64_INS_LDRSB: -1,
    ARM64_INS_LDURSB: -1,
    ARM64_INS_LDRH: 2,
    ARM64_INS_LDURH: 2,
    ARM64_INS_LDRSH: -2,
    ARM64_INS_LDURSH: -2,
    ARM64_INS_LDURSW: -4,
    ARM64_INS_LDRSW: -4,
    ARM64_INS_LDUR: None,
    ARM64_INS_LDR: None,
    ARM64_INS_LDTRB: 1,
    ARM64_INS_LDTRSB: -1,
    ARM64_INS_LDTRH: 2,
    ARM64_INS_LDTRSH: -2,
    ARM64_INS_LDTRSW: -4,
    ARM64_INS_LDTR: None,
    ARM64_INS_LDXRB: 1,
    ARM64_INS_LDXRH: 2,
    ARM64_INS_LDXR: None,
    ARM64_INS_LDARB: 1,
    ARM64_INS_LDARH: 2,
    ARM64_INS_LDAR: None,
}

AARCH64_SINGLE_STORE_INSTRUCTIONS module-attribute ¤

AARCH64_SINGLE_STORE_INSTRUCTIONS: dict[int, int | None] = {
    ARM64_INS_STRB: 1,
    ARM64_INS_STURB: 1,
    ARM64_INS_STRH: 2,
    ARM64_INS_STURH: 2,
    ARM64_INS_STUR: None,
    ARM64_INS_STR: None,
    ARM64_INS_STTRB: 1,
    ARM64_INS_STTRH: 2,
    ARM64_INS_STTR: None,
    ARM64_INS_STLRB: 1,
    ARM64_INS_STLRH: 2,
    ARM64_INS_STLR: None,
}

AARCH64_EXCLUSIVE_STORE_INSTRUCTIONS module-attribute ¤

AARCH64_EXCLUSIVE_STORE_INSTRUCTIONS = {
    ARM64_INS_STXRB: 1,
    ARM64_INS_STXRH: 2,
    ARM64_INS_STXR: None,
    ARM64_INS_STLXRB: 1,
    ARM64_INS_STLXRH: 2,
    ARM64_INS_STLXR: None,
}

CONDITIONAL_SELECT_INSTRUCTIONS module-attribute ¤

CONDITIONAL_SELECT_INSTRUCTIONS = {
    ARM64_INS_CSEL,
    ARM64_INS_CSINC,
    ARM64_INS_CSINV,
    ARM64_INS_CSNEG,
    ARM64_INS_CSET,
    ARM64_INS_CSETM,
    ARM64_INS_CINC,
    ARM64_INS_CINV,
    ARM64_INS_CNEG,
}

AARCH64_EMULATED_ANNOTATIONS module-attribute ¤

AARCH64_EMULATED_ANNOTATIONS = CONDITIONAL_SELECT_INSTRUCTIONS | {
    ARM64_INS_SXTB,
    ARM64_INS_SXTH,
    ARM64_INS_SXTW,
    ARM64_INS_UXTB,
    ARM64_INS_UXTH,
    ARM64_INS_UXTW,
    ARM64_INS_RBIT,
    ARM64_INS_CLS,
    ARM64_INS_CLZ,
    ARM64_INS_BFXIL,
    ARM64_INS_UBFIZ,
    ARM64_INS_UBFM,
    ARM64_INS_UBFX,
    ARM64_INS_SBFIZ,
    ARM64_INS_SBFM,
    ARM64_INS_SBFX,
    ARM64_INS_BFI,
    ARM64_INS_NEG,
    ARM64_INS_NEGS,
    ARM64_INS_REV,
    ARM64_INS_BIC,
    ARM64_INS_BICS,
}

AARCH64_BIT_SHIFT_MAP module-attribute ¤

AARCH64_BIT_SHIFT_MAP: dict[int, Callable[[int, int, int], int]] = {
    ARM64_SFT_LSL: logical_shift_left,
    ARM64_SFT_LSR: logical_shift_right,
    ARM64_SFT_ASR: arithmetic_shift_right,
    ARM64_SFT_ROR: rotate_right,
}

AARCH64_EXTEND_MAP module-attribute ¤

AARCH64_EXTEND_MAP: dict[int, Callable[[int], int]] = {
    ARM64_EXT_UXTB: lambda x: x & 1 << 8 - 1,
    ARM64_EXT_UXTH: lambda x: x & 1 << 16 - 1,
    ARM64_EXT_UXTW: lambda x: x & 1 << 32 - 1,
    ARM64_EXT_UXTX: lambda x: x,
    ARM64_EXT_SXTB: lambda x: to_signed(x, 8),
    ARM64_EXT_SXTH: lambda x: to_signed(x, 16),
    ARM64_EXT_SXTW: lambda x: to_signed(x, 32),
    ARM64_EXT_SXTX: lambda x: to_signed(x, 64),
}

AARCH64_MATH_INSTRUCTIONS module-attribute ¤

AARCH64_MATH_INSTRUCTIONS = {
    ARM64_INS_ADD: "+",
    ARM64_INS_ADDS: "+",
    ARM64_INS_SUB: "-",
    ARM64_INS_SUBS: "-",
    ARM64_INS_AND: "&",
    ARM64_INS_ANDS: "&",
    ARM64_INS_ORR: "&",
    ARM64_INS_ASR: ">>s",
    ARM64_INS_ASRV: ">>s",
    ARM64_INS_EOR: "^",
    ARM64_INS_LSL: "<<",
    ARM64_INS_LSLV: "<<",
    ARM64_INS_LSR: ">>",
    ARM64_INS_LSRV: ">>",
    ARM64_INS_UDIV: "/",
    ARM64_INS_SDIV: "/",
    ARM64_INS_SMULH: "*",
    ARM64_INS_SMULL: "*",
    ARM64_INS_UMULH: "*",
    ARM64_INS_UMULL: "*",
    ARM64_INS_MUL: "*",
}

assistant module-attribute ¤

assistant = DisassemblyAssistant('aarch64')

DisassemblyAssistant ¤

DisassemblyAssistant(architecture: str)

Bases: DisassemblyAssistant

Methods:

Attributes:

annotation_handlers instance-attribute ¤

annotation_handlers: dict[
    int, Callable[[PwndbgInstruction, Emulator], None]
] = {
    ARM64_INS_MOV: _common_move_annotator,
    ARM64_INS_MOVK: _common_generic_register_destination,
    ARM64_INS_ADR: _common_generic_register_destination,
    ARM64_INS_ADRP: _handle_adrp,
    ARM64_INS_CMP: _common_cmp_annotator_builder("cpsr", "-"),
    ARM64_INS_CMN: _common_cmp_annotator_builder("cpsr", "+"),
    ARM64_INS_TST: _common_cmp_annotator_builder("cpsr", "&"),
    ARM64_INS_CCMP: _common_cmp_annotator_builder("cpsr", ""),
    ARM64_INS_CCMN: _common_cmp_annotator_builder("cpsr", ""),
}

assistants class-attribute instance-attribute ¤

assistants: dict[str, DisassemblyAssistant] = {}

op_handlers instance-attribute ¤

op_handlers: dict[
    int, Callable[[PwndbgInstruction, EnhancedOperand, Emulator], int | None]
] = {
    CS_OP_IMM: _parse_immediate,
    CS_OP_REG: _parse_register,
    CS_OP_MEM: _parse_memory,
}

op_names instance-attribute ¤

op_names: dict[
    int, Callable[[PwndbgInstruction, EnhancedOperand], str | None]
] = {
    CS_OP_IMM: _immediate_string,
    CS_OP_REG: _register_string,
    CS_OP_MEM: _memory_string,
}

for_current_arch staticmethod ¤

for_current_arch() -> DisassemblyAssistant

enhance staticmethod ¤

enhance(instruction: PwndbgInstruction, emu: Emulator = None) -> None

can_reason_about_process_state ¤

can_reason_about_process_state(instruction: PwndbgInstruction) -> bool

Determine if the program counter of the process equals the address of the instruction being enhanced. If so, it means we can safely reason and read from registers and memory to enhance values that we can add to the annotation string. This becomes relevent when NOT emulating, and is meant to allow more details when the PC is at the instruction being enhanced

dump ¤

dump(instruction: PwndbgInstruction)

Debug-only method.

resolve_condition ¤

resolve_condition(condition: int, cpsr: int) -> InstructionCondition

Given a condition and the NZCV flag bits, determine when the condition is satisfied

The condition is a Capstone constant